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MA007A 3-in-1 8-bit serial to parallel latch this document contains information on a new product under developm ent by megawin. megawin reserves the right to change or disco ntinue this product without notice. ? megawin technology co., ltd. 2006 all rights reserved. 2005/11 version a1 megawin features ? three 8-bit serial input ? three 8-bit parallel output ? operation voltage: 2.0v to 5.7v ? storage register with 3-state outputs ? shift register with direct clear ? 5 mhz (typical) shift out frequency ? output capability: ? parallel outputs; bus driver ? serial output; standard selection information MA007Ah MA007Ap MA007Ad MA007Af package / dice dice 44-plcc 48-lqfp 44-pqfp parallel output 24 pins sink current 20ma application field serial-to-parallel data conversion remote control holding register
2 MA007A technical summary megawin general description the ma007 are high-speed si-gate cmos devices. there are three groups 8-stage serial shift register with a storage register and 3-state outputs in ma007. the shift register and storage register have separate clocks. data is shifted on the positive-going transitions of the sclk input. the data in each register is transferred to the storage register on a positive-going transition of the pclk input. if both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. the shift register has a serial input (d inx ) and a serial standard output (d outx ) for cascading. it is also provided with asynchronous reset (active low) for all 8 stages shift register. the storage register has 8 parallel 3-state bus driver outputs. data in the storage register appears at the output whenever the output enable input (/oe) is low. pad description pad no. pad name i/o description 1 /oe i output enable (active low) 2 pclk i parallel register clock input 3 /sclr i serial register reset (active low) 4 sclk i shift register clock input 5, 6, 7 d in0 , d in1 , d in2 i serial data input 10, 9, 8 d out0 , d out1 , d out2 o serial data output 20 to 13 q 20 to q 27 o parallel data group 2 output 29 to 22 q 10 to q 17 o parallel data group 1 output 38 to 31 q 00 to q 07 o parallel data group 0 output 12, 30, 40 v cc p positive supply voltage 11, 21, 39, 41 gnd p power ground (0 v)
megawin MA007A technical summary 3 block diagram 8-stage shift register 8-bit storage register 3-state outputs 8-stage shift register 8-bit storage register 3-state outputs 8-stage shift register 8-bit storage register 3-state outputs pclk /oe /sclr sclk din0 din1 din2 dout0 dout1 dout2 10 8 9 4 3 2 1 5 6 7 20 13 14 19 18 17 16 15 q20 q21 q22 q23 q24 q25 q26 q27 22 23 24 29 28 27 26 25 q10 q11 q12 q13 q14 q15 q16 q17 32 33 34 31 38 37 36 35 q00 q01 q02 q03 q04 q05 q06 q07
4 MA007A technical summary megawin function description function table inputs outputs sclk pclk /oe /sclr d inx d outx q xn functon x x l l x l nc a low level on /sclr only affects the shift registers x l l x l l empty shift register loaded into storage register x x h l x l z shift register clear. parallel outputs in high-impedance off-state x l h h qx6? nc logic high level shifted into shift register stage 0. contents of all shift register stages shifted through, e.g. previous state of stage 6 (i nternal qx6?) appears on the serial output (d outx ) x l h x nc qxn? contents of shift register stages (internal qxn?) are transferred to the storage register and parallel output stages l h x qx6? qxn? contents of shift register shifted through. previous contents of the shift register are transferred to the storage register and the parallel output stages. notes h = high voltage level; l = low voltage level = low-to-high transition; = high-to-low z = high-impedance off-state; nc = no change x = don?t care.
megawin MA007A technical summary 5 application circuit 1 2 3 4 56 a b c d 6 5 4 3 2 1 d c b a title number revision size b date: 28-mar-2005 sheet of file: e:\user\feng\project\datasheet\MA007A\led_clock_asic2_ap.ddb drawn by: spk2 36 avdd 35 spk1 34 agnd 33 p1.7 32 p1.6 31 p1.5 30 p1.4 29 p1.3 28 p1.2 27 p1.1 26 p1.0 25 p2.7 24 p2.6 23 x32i 8 p0.0 9 p0.1 10 p0.2 11 p0.3 12 p0.4 13 p0.5 14 vdd 1 osco 2 osci 3 gnd 4 res 5 test 6 x32o 7 p2.5 22 p2.4 21 p2.3 20 p2.2 19 p2.1 18 p2.0 17 p0.7 16 p0.6 15 u1 mlc031a/021a/017a_cob vcc vcc c11 0.1uf c12 0.1uf vcc vcc oe 1 pclk 2 din2 7 sclr 3 sclk 4 q10 29 q11 28 q12 27 q13 26 q14 25 q15 24 q16 23 q17 22 din0 5 din1 6 dout0 10 dout2 8 dout1 9 q27 13 q26 14 q25 15 q24 16 q23 17 q22 18 q21 19 q20 20 vcc 12 gnd 11 gnd 21 vcc 30 q00 38 q01 37 q02 36 q03 35 q04 34 q05 33 q06 32 q07 31 gnd 39 vcc 40 opt 41 u2 MA007A_cob c5 100pf ic_vcc c9 0.1uf c4 47uf r3 620 q2 8050s vcc r1 680k spk1 spk1 p0.0 ic_vcc spk1 8 ohm @4mhz x1 32.768khz c6 20pf c7 20pf r2 8.2k li-battery 3.0v q1 8050s c8 0.1uf vcc r10 100 * 8 r13 r14 r15 r16 r12 r17 r11 r27 100 * 8 r22 r23 r24 r25 r21 r26 r20 led led r37 100 * 8 r32 r33 r34 r35 r31 r36 r30 q5 8550d q6 8550d r5 1k r6 1k vcc vcc vcc d6 1n4148 d5 1n60p + c2 470uf c3 0.1uf v+ (ext) p1.0 p1.1 p1.0 p1.1 led led led led q7 8550d q8 8550d r7 1k r8 1k vcc vcc label_c1 label_c2 label_c1 label_c2 gnd
6 MA007A technical summary megawin pad assignment q27 vcc dout0 dout1 dout2 din2 din1 din0 sclk /sclr pclk /oe 11 12 13 14 15 16 17 18 19 20 21 23 24 25 10 9 8 7 6 5 4 3 2 1 (0,0) q20 q21 q22 q23 q24 q25 q26 gnd q10 q17 q16 q15 q14 q13 q12 q11 q00 gnd q07 q06 q05 q04 q03 q02 q01 vcc gnd 39 38 37 36 35 34 33 32 31 30 29 28 27 26 41 40 gnd vcc 22
megawin MA007A technical summary 7 absolute maximum rating parameter rating unit supply voltage to ground potential -0.3 to +6.0 v applied input / output vo ltage -0.3 to +6.0 v power dissipation 500 mw ambient operating temperature 0 to +70 c storage temperature -55 to +150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. dc characteristics (v cc -gnd = 5.0v, ta = 25 c; unless otherwise specified) parameter sym. conditions min. typ. max. unit op. voltage v cc - 2.0 5.0 6.0 v op. current i op no load (ext.-v) - 4.0 16.0 a input high voltage v ih - 0.7 v dd - v dd v input low voltage v il - 0 - 0.3v dd v d outx s ink current i ol0 v ol = 0.4v - 3.0 4.5 ma d outx drive current i oh0 v oh = 4.5v - 1.5 2.5 ma v ol = 0.4v - 18 27 ma q x0 to q x7 sink current i ol1 v ol = 0.4v, v cc = 6.0v - 20 32 ma v oh = 4.5v - 2.7 3.5 ma q x0 to q x7 drive current i oh1 v oh = 5.4v, v cc = 6.0v - 3.0 5.0 ma all output sink current i ol2 v ol = 0.4v - 16 24 ma all output drive current i oh2 v oh = 4.5v - 8 12 ma total output sink current i ol3 v ol = 0.4v - 384 576 ma total output drive current i oh3 v oh = 4.5v - 192 288 ma
8 MA007A technical summary megawin ac characteristics (vcc-gnd = 5.0v, ta = 25 c; unless otherwise specified) parameter sym. conditions min. typ. max. unit maximum clock pulse frequency (sclk, pclk) f max 50 % duty cycle - 2.5 5 mhz t phl1 t plh1 sclk to d outx , c l = 15 pf - 95 195 ns t phl2 t plh2 pclk to q xn , c l = 15 pf - 100 200 ns propagation delay t phl3 /sclr to d outx , c l = 15 pf - 100 200 ns t su1 din to sclk 10 - - ns t su2 sclk to pclk 100 - - ns setup time t su3 sclk to pclk - 5 10 ns t w1 sclk 25 - - ns t w2 pclk 25 - - ns pulse width t w3 /sclr 25 - - ns tri-state output enable time t pzh t pzl /oe to q xn - 100 200 ns tri-state output disable time t phz t plz /oe to q xn - 100 200 ns hold time t h din to sclk 5 - - ns removal time t rem /sclr to sclk 10 - - ns
megawin MA007A technical summary 9 system timing sclk to d outx propagation delay waveforms sclk d outx 50% 1/f max t w1 t plh1 t phl1 pclk to q xn propagation delay and setup time waveforms pclk q xn 50% 1/f max t w2 t plh2 t phl2 t su2 sclk
10 MA007A technical summary megawin sclk and pclk are connected together to q xn-1 propagation delay and setup time waveforms pclk q xn-1 50% 1/f max t w2 t plh2 t phl2 t su3 sclk pclk to q xn propagation delay and setup time waveforms d inx d outx 50% t phl3 t su1 sclk t h /sclr t w3 t rem
megawin MA007A technical summary 11 tri-state enable/disable time waveforms q xn low-to-off off-to-low t plz /oe q xn high-to-off off-to-high t pzl t pzh t phz outputs disable outputs enable outputs enable
12 MA007A technical summary megawin package information MA007Ae 48 pin pdip (600mil) configuration din0 din1 din2 dout2 dout1 dout0 gnd vcc q27 q26 q25 q24 q23 q22 q21 q20 gnd q17 q16 q15 q14 nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 q10 q11 q12 q13 nc nc nc nc q01 q02 q03 q04 q05 q06 q07 vcc sclk /sclr pclk /oe gnd vcc gnd q00 48-pdip (600 mil) 48 pin pdip package dimension
megawin MA007A technical summary 13 MA007Ap 44 pin plcc configuration vcc q27 q26 q25 7 8 9 10 q24 q23 q22 q21 q20 gnd 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 29 30 31 32 33 34 35 36 37 38 39 q10 q17 q16 q15 q14 nc nc nc q13 q12 q11 vcc q07 q06 q05 q04 q03 q02 q01 q00 gnd vcc gnd /oe pclk /sclr sclk din0 din1 din2 dout2 dout1 dout0 gnd 44 pin plcc package dimension
14 MA007A technical summary megawin MA007Ad 48 pin lqfp configuration vcc q27 q26 q25 1 2 3 4 q24 q23 q22 q21 q20 gnd 5 6 7 8 9 10 11 12 q17 q16 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 25 26 27 28 29 30 31 32 33 34 35 36 q15 q14 nc nc nc nc nc nc nc q13 q12 q11 q10 vcc q07 q06 q05 q04 q03 q02 q01 q00 gnd vcc gnd /oe pclk /sclr sclk din0 din1 din2 dout2 dout1 dout0 gnd 48 pin lqfp package dimension
megawin MA007A technical summary 15 MA007Af 44 pin pqfp configuration gnd /oe 1 2 3 4 pclk /sclr sclk din0 din1 din2 5 6 7 8 9 10 11 dout2 dout1 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 23 24 25 26 27 28 29 30 31 32 33 gnd vcc q27 q26 q25 q24 q23 q22 q21 q20 gnd q17 q16 q15 q14 nc nc nc q12 q11 q10 vcc q07 q06 q05 q04 q03 q02 q01 q00 gnd vcc dout0 q13 44 pin pqfp package dimension
16 MA007A technical summary megawin notes: vision history version date page description a1 nov. 2005 initial issue.

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